In power MOSFETs (metal oxide semiconductor field effect transistors) with dual poly field plate trench technology, the gate electrode is above the field plate electrode and the charge between the gate and drain (Qgd) is defined by the sidewall overlap of the gate electrode to the silicon part of the device below the body. In the case of a stand-alone gate electrode concept i.e. no field electrode in the same trench as the gate electrode, the overlap between the gate electrode and the silicon part of the device below the body is increased due to the overlap between the bottom of the gate trench and the silicon. The increase in Qgd can be significant. Increased Qgd results in reduced overall switching performance.
One conventional approach for addressing this problem involves forming a thick bottom oxide at the bottom of the gate electrode trench using a deposition method such as HDP (high-density plasma) chemical vapor deposition which creates a thicker oxide at the bottom of the trench as compared to along the trench sidewalls. Another approach involves damaging the silicon at the bottom of the trench using a damage implant to achieve an enhanced oxidation rate. Yet another approach involves protecting the sidewall and top part of the trench with a single protective layer while removing the protective layer at the bottom of the trench so it can be oxidized. In the last approach, it is difficult to ensure that the protective layer is completely removed at the bottom of the trench while also ensuring that the other parts of the trench (sidewall and top) are fully protected from the trench bottom oxidation process. The last approach is particularly difficult to implement over a wide process window because small device features and high aspect ratios require the use of a very thin protective layer which exasperates the problem.